Method and apparatus for segmenting memory based upon bandwidth of a data communication platform

ABSTRACT

A method and apparatus for combining cost effectiveness of data signal ports sharing a common memory storage device with reliable data signal communication of data signal ports each having a dedicated memory storage device. In one embodiment, data signals are received at a number of data signal ports of a data signal communication platform. A data signal bandwidth capability of a memory storage device of the data communication platform is determined. Once the data signal bandwidth capability of the memory storage device is determined, the memory storage device is segmented to improve utilization of the data signal bandwidth capability. As a result, cost effectiveness of data signal ports sharing a common memory storage device and reliability of data signal communication of data signal ports each having a dedicated memory storage device is combined.

FIELD OF THE INVENTION

[0001] The present invention pertains to the field of electronicdevices. More particularly, this invention relates to networkcommunications.

BACKGROUND

[0002] As more computer devices are networked, communication between thecomputer devices have become faster. Faster communication involvestransmitting and receiving large amounts of data signals betweennetworked devices. Often, the rate at which the data signals arereceived, processed, and transmitted may determine the speed of thecommunication.

[0003] The data communication platform may be implemented in applicationspecific integrated circuits (ASICs). Data signal ports are incorporatedinto the data communication platform through which the data signals arereceived and transmitted. Each data signal port may be both an inputport and an output port, and therefore, two data signal ports couldpossibly receive and transmit data signals as four input/output pairs.Through these data signal ports, data signals are received, processed bythe data communication platform, and the data signals are transmitted totheir destination. The processing of the data signals by the datacommunication platform is commonly known as switching, and therefore,one example of a data communication platform implemented in ASICs is anethernet switch engine.

[0004] The data communication platform usually includes a limited numberof data signal ports. Often times, the data signal ports may receivedata signals while the data signal ports to transmit the data signals totheir destinations are occupied, thereby causing a “traffic jam” withinthe data communication platform. In order to control this “traffic jam”of data signals from preventing communication of the data signals, thedata signals are temporarily stored in a memory storage device includedwith the data communication platform.

[0005] The memory storage device, for example, a dynamic random accessmemory (DRAM) device, may be used as a buffer, i.e., the data signalsare temporarily stored in the memory storage device until a data signalport for transmission of the data signal is free to transmit the datasignals to their destinations. A measure of the rate at which datasignals are deposited and retrieved from the memory storage device maybe known as a data signal bandwidth, an access rate of the memorystorage device.

[0006] Commonly, there are two methods for implementing datacommunication platforms. One method employs the use of a shared memorystorage device, where one memory storage device is utilized by a numberof data signal ports of the data communication platform. This methodrelies on the fact that all of the data signal ports might not be activein receiving and transmitting data signals at the same time. The sharedmemory storage device is cost effective, but if at some point, all ofthe data signal ports are active, the memory storage device will nothave enough capacity to accommodate all of the data signals beingreceived and transmitted by the data communication platform because thememory storage devices are of a limited capacity as part of the costeffectiveness. Some data signals may be lost or sent back to the sendercausing unreliable data signal communication.

[0007] Another method employs the use of a dedicated memory storagedevice for each data signal port. This method provides reliable datasignal communication because each memory storage device will have enoughcapacity to accommodate receiving and transmitting the data signal ateach data signal port. However, depending upon the number of data signalports, this method will require a large amount of memory because eachdata signal port would have its own dedicated memory storage devicededicated to the data signal port. Additionally, the dedicated memorystorage device method is not as cost effective as the shared memorystorage device method because if the any of the data signal ports areinactive, the memory storage device would not be utilized for thoseinactive data signal port.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention is illustrated by way of example and not byway of limitation in the figures of the accompanying drawings, in whichthe like references indicate similar elements and in which:

[0009]FIG. 1 illustrates a block diagram of one embodiment of thepresent invention for combining cost effectiveness of data signal portssharing a common memory storage device with reliable data signalcommunication of data signal ports each having dedicated memory storagedevices;

[0010]FIG. 2 illustrates an operational flow of one embodiment of thepresent invention; and

[0011]FIG. 3 illustrates a computer system upon which an embodiment ofthe present invention can be implemented.

DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following detailed description, numerous specific detailsare set forth in order to provide a thorough understanding of thepresent invention. However, those skilled in the art will understandthat the present invention may be practiced without these specificdetails, that the present invention is not limited to the depictedembodiments, and that the present invention may be practiced in avariety of alternate embodiments. In other instances, well knownmethods, procedures, components, and circuits have not been described indetail.

[0013] Parts of the description will be presented using terminologycommonly employed by those skilled in the art to convey the substance oftheir work to others skilled in the art. Also, parts of the descriptionwill be presented in terms of operations performed through the executionof programming instructions. As well understood by those skilled in theart, these operations often take the form of electrical, magnetic, oroptical signals capable of being stored, transferred, combined, andotherwise manipulated through, for instance, electrical components.

[0014] Various operations will be described as multiple discrete stepsperformed in turn in a manner that is helpful in understanding thepresent invention. However, the order of description should not beconstrued as to imply that these operations are necessarily performed inthe order they are presented, or even order dependent. Lastly, repeatedusage of the phrase “in one embodiment” does not necessarily refer tothe same embodiment, although it may.

[0015] As discussed more fully below, the present invention provides amethod to combine cost effectiveness of data signal ports sharing acommon memory storage device with reliable data signal communication ofdata signal ports each having a dedicated memory storage device.

[0016] In general, embodiments of the present invention determines adata signal bandwidth capability for a memory storage device includedwith a data communication platform, and the memory storage device issegmented to increase utilization of the data signal bandwidthcapability of the memory storage device included with the datacommunication platform.

[0017]FIG. 1 illustrates a block diagram of one embodiment of thepresent invention for combining cost effectiveness of data signal portssharing a common memory storage device with reliable data signalcommunication of data signal ports each having dedicated memory storagedevices. Shown in FIG. 1 is a data communication platform 100 thatreceives, processes, and transmits data signals 101. In one embodiment,the data communication platform 100 may be a network switch engine,where the network switch engine may be implemented as applicationspecific integrated circuits (ASICs). It should be appreciated by oneskilled in the art that data signals 101 may be in the form of datasignal packets, commonly utilized in data communication platforms.

[0018] Shown in FIG. 1, data signals are received at the datacommunication platform 100 by a number of data signal ports 102functioning to receive the data signals 101. The data signals 101 arethen processed by a filter component 103, which may involve determiningan origin and a destination of the data signal 101.

[0019] In FIG. 1, after being processed in the filter component 103, thedata signal 101 is received by a queue system 105. Included with thequeue system 105 is a multiplexer 106, a memory storage device 107, anumber of segments 110-118 of the memory storage device 107, and anoutput queue component 120. The multiplexer 106 multiplexes the datasignals to each of the number of segments 110-118. The output queuecomponent 120 queues the data signals 101 from the memory storage device107 for transmission to their destinations (not shown), such asnetworked computer devices, through the number of data signal ports 120functioning to transmit the data signals 101. In one embodiment, thememory storage device 107 may be a dynamic random access memory (DRAM)device. Additionally, the memory storage device 107 is a shared memorystorage device, where all of the data signal ports 102 share the memorystorage device 107.

[0020] In one embodiment, the data communication platform 100 may be anetwork switch engine, in particular, an ethernet switch engine. Thenumber of data signal ports 102 may be twenty four data signal ports,and each data signal port may be capable of a particular data signalcommunication rate, or commonly known as a particular bit rate, of 1Gigabit/second.

[0021] The memory storage device 107 has a random access cycle timerelated to the type of memory storage device. A data signal bandwidthcapability of the memory storage device 107 is determined from therandom access cycle time of the memory storage device 107. The datasignal bandwidth capability may be a rate at which there may be moredata signals 101 going into the memory storage device 107 than datasignals 101 leaving. This situation may cause unreliable data signalcommunication through the data communication platform 100.

[0022] The memory storage device 107 receives data signals at a cellrate, where the cell may be a manner in which packets are dividedaccording to a particular size depending on a network technology. Thecell rate is related to the number of data signal ports 102, the datasignal communication rate of the data signal ports 102, and a size ofthe data signals or data signal packet sizes, received by the memorystorage device 107. The cell rate determines a rate at which datasignals 101 are received by the data communication platform 100 forreceiving, processing, and transmitting the data signals 101 to theirdestinations.

[0023] As shown in FIG. 1, in one embodiment, the memory storage device107 is segmented into segments 110-118. The number of segments 110-118may be determined by determining the data signal bandwidth capabilityfor the memory storage device 107 and determining the cell rate receivedby the memory storage device 107 as described above. The memory storagedevice 107 is segmented so that each of the segments 110-118 have a datasignal bandwidth capability substantially similar to the data signalbandwidth capability of the memory storage device 107. However, each ofthe segments 110-118 is dedicated to a particular number of data signalports 102 at any given time, as illustrated in a chart below. CHART 1INPUT OUTPUT PORT PORT 0-7 8-15 16-23 0-7 Segment 110 Segment 111Segment 112  8-15 Segment 113 Segment 114 Segment 115 16-23 Segment 116Segment 117 Segment 118

[0024] In Chart 1, twenty four data signal ports are utilized to receiveand transmit data signals 101 by the data communication platform 100.The data signal ports 102 may be either operating to receive datasignals 101 (input ports) or transmit data signals 101 (output ports).As shown in Chart 1, each of the segments 110-118 is dedicated to aparticular number of data signal ports. In one embodiment, each segment110-118 is dedicated to eight data signal ports operating as input portsand eight data signal ports operating as output ports out of a total oftwenty four data signal ports, and therefore, the twenty four datasignal ports are utilized in three pairs of eight. However, each segment110-118 has substantially similar data signal bandwidth capability asthe memory storage device 107, as discussed above. A segmented memorystorage device, in particular, a memory storage device shared by anumber of data signal ports, increases utilization of the data signalbandwidth capability of the memory storage device by reducing the numberof data signal ports supported by the data signal bandwidth capabilityof the memory storage device.

[0025] As a result, determining a data signal bandwidth capability of amemory storage device of a data communication platform and segmentingthe memory storage device to increase utilization of the data signalbandwidth capability combines cost effectiveness of data signal portssharing a common memory storage device with reliable data signalcommunication of data signal ports each having a dedicated memorystorage device.

[0026] An example of one embodiment for segmenting a memory storagedevice, in particular, a memory storage device shared by a number ofdata signal ports, increasing utilization of the data signal bandwidthcapability of the memory storage device by reducing the number of datasignal ports supported by the data signal bandwidth capability of thememory storage device is as follows:

[0027] Number of bits per byte:

8 bits/byte

[0028] Data communication platform with number of data signal ports:

24 data signal port ethernet switch engine implemented as ASICs

[0029] Bit rate of each data signal port:

1 Gigabits/second (1×10⁹ bits/second)

[0030] Particular number of required cells based on an ethernet frame(packet) size to minimize the number of bytes required by the cells:

cell size≧148 bytes

[0031] Particular minimum data signal packet size:

64 bytes

[0032] Preamble of data signal packet size:

8 bytes

[0033] Inter-frame gap of data signal packet size:

12 bytes

[0034] Memory storage device:

Imbedded DRAM in ASICs

[0035] Particular random access time:

30 nanoseconds (30×10⁻⁹ seconds)

[0036] Data signal bandwidth capability for particular DRAM (depended onthe particular memory storage device technology):

(Particular random access time)⁻¹=1/(30×10⁻⁹)=33×10⁶cells/second  Relationship 1

[0037] Data signal packet size:

(particular minimum data signal packet size)+(preamble of data signalpacket size)+(Inter-frame gap of data signal packet size)=(64 bytes)+(8bytes)+(12 bytes)=84 bytes  Relationship 2

[0038] Cells received by the memory storage device rate: $\begin{matrix}{{\frac{\begin{matrix}{\left( {{number}\quad {of}\quad {data}\quad {signal}\quad {ports}} \right)\left( {{bit}\quad {rate}\quad {for}} \right.} \\\left. {{each}\quad {data}\quad {signal}\quad {port}} \right)\end{matrix}}{\quad {\left( {{number}\quad {of}\quad {bits}\quad {per}\quad {byte}} \right)\left( {{data}\quad {signal}\quad {packet}\quad {size}} \right)}\quad} = {\frac{(24)\left( {1 \times 10^{9}\quad {bits}\text{/}\sec} \right)}{\left( {8\quad {bits}\text{/}{byte}} \right)\left( {84\quad {bytes}} \right)} = \underset{\_}{35.7 \times 10^{6}{cells}\text{/}{second}}}}\quad} & {{Relationship}\quad 3}\end{matrix}$

[0039] Data signal bandwidth capability for read/write into the memorystorage device:

twice the transaction (reading and writing) cells received by the memorystorage device rate=(2)(35.7×10⁶ cells/second)=71.40×10⁶cells/second  Relationship 4

[0040] As shown in the example embodiment, the determination of the datasignal bandwidth for read/write into the memory storage device (Rel. 4)is larger than the determination of the data signal bandwidth capabilityfor particular DRAM (Rel. 1). This may cause the memory storage deviceto receive more data signals than the memory storage device cantransmit, thereby data signals may be either lost or the datacommunication by the data communication may be unreliable.

[0041] However, referring back to Chart 1 and FIG. 1, the memory storagedevice 107 is segmented into nine segments 110-118. Applying Rel. 3 tothe segmented memory storage device 107 results in the followingdetermination: $\begin{matrix}{\begin{matrix}{\quad \left\lbrack \left( {\left( {{number}\quad {of}\quad {data}\quad {signal}\quad {ports}} \right)/} \right. \right.} \\\left. \quad \left( {{number}\quad {of}\quad {input}\text{/}{output}\quad {data}\quad {signal}\quad {port}\quad {pairs}} \right) \right) \\\left. \quad \left( {{bit}\quad {rate}\quad {for}\quad {each}\quad {data}\quad {signal}\quad {port}} \right) \right\rbrack \\\left\lbrack \left( {{number}\quad {of}\quad {bits}\quad {per}\quad {byte}} \right) \right.\end{matrix} = \quad {\frac{\left( {\left( {24/(3)} \right)\left( {1 \times 10^{9}{bits}\text{/}{second}} \right.} \right.}{\left( {8\quad {bits}\text{/}{byte}} \right)\left( {84\quad {bytes}} \right)} = {11.9 \times 10^{6}{cells}\text{/}{second}}}} & \text{Determination~~~1}\end{matrix}$

[0042] In order to determine the data signal bandwidth capability forread/write into the memory storage device with the segments, Rel 4 isapplied as follows:

twice the transaction (reading and writing) cells received by the memorystorage device rate=(2)(11.9×10⁶ cells/second)=23.8×10⁶cells/second  Determination 2

[0043] Because the memory storage device 107 is segmented, the datasignal bandwidth capability of 23.8×10⁶ cells/second (Det. 1) of eachsegment 110-118 is less than 33×10⁶ cell/second (Rel. 1), the datasignal bandwidth capability for the memory storage device, DRAM. As aresult of the segmented memory storage device, even though all of thedata signal ports may be utilized, the utilization of the data signalbandwidth capability of the memory storage device shared by the datasignal ports is improved.

[0044] Thus in the example embodiment, determining a data signalbandwidth capability of a memory storage device of a data communicationplatform and segmenting the memory storage device to increaseutilization of the data signal bandwidth capability combines costeffectiveness of data signal ports sharing a common memory storagedevice with reliable data signal communication of data signal ports eachhaving a dedicated memory storage device.

[0045]FIG. 2 illustrates an operational flow of one embodiment of thepresent invention. In FIG. 2 data signals are received at a number ofdata signal ports of a data communication platform, 210. A data signalbandwidth capability for a memory storage device of the datacommunication platform is determined, 215. Once the data signalbandwidth capability for the memory storage device of the datacommunication platform is determined, the memory storage device issegmented to improve the utilization of the data signal bandwidthcapability of the memory storage device, 220. Accordingly, theoperational flow of FIG. 2 provides a method to combine costeffectiveness of data signal ports sharing a common memory storagedevice with reliable data signal communication of data signal ports eachhaving a dedicated memory storage device in accordance with the presentinvention.

[0046]FIG. 3 illustrates a computer system 300 upon which an embodimentof the present invention can be implemented. The computer system 300includes a processor 301 that processes data signals. The processor 301may be a complex instruction set computer (CISC) microprocessor, areduced instruction set computing (RISC) microprocessor, a very longinstruction word (VLIW) microprocessor, a processor implementing acombination of instruction sets, or other processor device. FIG. 3 showsan example of the present invention implemented on a single processorcomputer system 300. However, it is understood that the presentinvention may be implemented in a computer system having multipleprocessors. The processor 301 is coupled to a CPU bus 310 that transmitsdata signals between processor 301 and other components in the computersystem 300.

[0047] The computer system 300 includes a memory 313. The memory 313 maybe a dynamic random access memory (DRAM) device, a synchronous directrandom access memory (SDRAM) device, or other memory device. The memory313 may store instructions and code represented by data signals that maybe executed by the processor 301.

[0048] A bridge/memory controller 311 is coupled to the CPU bus 310 andthe memory 313. The bridge/memory controller 311 directs data signalsbetween the processor 301, the memory 313, and other components in thecomputer system 300 and bridges the data signals between the CPU bus310, the memory 313, and a first I/O bus 320.

[0049] The first I/O bus 320 may be a single bus or a combination ofmultiple buses. As an example, the first I/O bus 320 may comprise aPeripheral Component Interconnect (PCI) bus, a Personal Computer MemoryCard International Association (PCMCIA) bus, a NuBus, or other buses.The first I/O bus 320 provides communication links between components inthe computer system 300. A network controller 321 is coupled to thefirst I/O bus 320. The network controller 321 links the computer system300 to a network of computers (not shown) and supports communicationamong the machines. A display device controller 322 is coupled to thefirst I/O bus 320. The display device controller 322 allows coupling ofa display device (not shown) to the computer system 300 and acts as aninterface between the display device and the computer system 300. Thedisplay device controller 322 may be a monochrome display adapter (MDA)card, a color graphics adapter (CGA) card, an enhanced graphics adapter(EGA) card, an extended graphics array (XGA) card or other displaydevice controller. The display device (not shown) may be a televisionset, a computer monitor, a flat panel display or other display device.The display device receives data signals from the processor 301 throughthe display device controller 322 and displays the information and datasignals to the user of the computer system 300.

[0050] A second I/O bus 330 may be a single bus or a combination ofmultiple buses. As an example, the second I/O bus 330 may comprise a PCIbus, a PCMCIA bus, a NuBus, an Industry Standard Architecture (ISA) bus,or other buses. The second I/O bus 330 provides communication linksbetween components in the computer system 300. A data storage device 331is coupled to the second I/O bus 330. The data storage device 331 may bea hard disk drive, a floppy disk drive, a CD-ROM device, a flash memorydevice or other mass storage device. A keyboard interface 332 is coupledto the second I/O bus 330. The keyboard interface 332 may be a keyboardcontroller or other keyboard interface. The keyboard interface 332 maybe a dedicated device or can reside in another device such as a buscontroller or other controller. The keyboard interface 332 allowscoupling of a keyboard (not shown) to the computer system 300 andtransmits data signals from a keyboard to the computer system 300. Anaudio controller 333 is coupled to the second I/O bus 330. The audiocontroller 333 operates to coordinate the recording and playing ofsounds.

[0051] A bus bridge 324 couples the first I/O bus 320 to the second I/Obus 330. The bus bridge 324 operates to buffer and bridge data signalsbetween the first I/O bus 320 and the second I/O bus 330.

[0052] In one embodiment, the data communication platform is implementedas network controller 321 to link the computer system 300 to a networkof computer devices (not shown). The data communication platformcombining cost effectiveness of data signal ports sharing a commonmemory storage device with reliable data signal communication of datasignal ports each having a dedicated memory storage device.

[0053] Thus, a method and apparatus for combining cost effectiveness ofdata signal ports sharing a common memory storage device with reliabledata signal communication of data signal ports each having a dedicatedmemory storage device is described.

[0054] Whereas many alterations and modifications of the presentinvention will be comprehended by one skilled in the art after havingread the foregoing description, it is to be understood that theparticular embodiments shown and described by way of illustration are inno way intended to be considered limiting. Therefore, references todetails for particular embodiments are not intended to limit the scopeof the claims.

What is claimed is:
 1. A method comprising: receiving a data signal at aplurality of data signal ports of data communication platform;determining a data signal bandwidth capability for a memory storagedevice of the data communication platform; and segmenting the memorystorage device to improve utilization of the data signal bandwidthcapability of the memory storage device of the data communicationplatform.
 2. The method of claim 1, wherein said determining comprisesdetermining the data signal bandwidth capability for a network switchengine, the network switch engine implemented as application specificintegrated circuits (ASICs).
 3. The method of claim 1, wherein saidsegmenting the memory storage device comprises determining a cell ratereceived by the memory storage device of the data communicationplatform.
 4. The method of claim 1, wherein said determining the datasignal bandwidth capability comprises determining a data signalbandwidth capability for a dynamic random access memory (DRAM) device.5. The method of claim 1, wherein said segmenting the memory storagedevice comprises segmenting the memory storage device based upon atleast a particular bit rate of the plurality of data signal ports. 6.The method of claim 1, wherein said segmenting the memory storage devicecomprises segmenting the storage device into a plurality of segmentseach having a data signal bandwidth capability substantially similar tothe data signal bandwidth capability of the memory storage device. 7.The method of claim 1, wherein said segmenting the memory storage deviceinto the plurality of segments comprises segmenting the memory storagedevice into a plurality of segments each dedicated to a particularnumber of the plurality of data signal ports of the data communicationplatform.
 8. An apparatus comprising: a data communication platform; aplurality of data signal ports, coupled to the data communicationplatform; and a memory storage device, coupled to the plurality of thedata signal ports, segmented to improve utilization of a data signalbandwidth capability of the memory storage device.
 9. The apparatus ofclaim 8, wherein said data communication platform comprises a networkswitch engine, the network switch engine implemented as applicationspecific integrated circuits (ASICs).
 10. The apparatus of claim 8,wherein said memory storage device comprises a dynamic random accessmemory (DRAM) device.
 11. The apparatus of claim 8, wherein saidplurality of data signal ports comprises a plurality of data signalports having a particular bit rate.
 12. The apparatus of claim 8,wherein said memory storage device comprises a memory storage devicesegmented into a plurality of segments each having a data signalbandwidth capability substantially similar to the data signal bandwidthcapability of the memory storage device.
 13. The apparatus of claim 8,wherein said memory storage device comprises segmenting the memorystorage device into a plurality of segments each dedicated to aparticular number of the plurality of data signal ports of the datacommunication platform.
 14. An article comprising: a storage mediumhaving stored therein a plurality of instructions that are machineexecutable, wherein when executed, said executing instructions operateto receive a data signal at a plurality of data signal ports of a datacommunication platform, determine a data signal bandwidth capability fora memory storage device of the data communication platform, and segmentthe memory storage device to improve utilization of the data signalbandwidth capability of the memory storage device of the datacommunication platform.
 15. The article of claim 14, wherein saidexecuting instructions operate to determine the data signal bandwidthcapability for a network switch engine, the network switch engineimplemented as application specific integrated circuits (ASICs).
 16. Thearticle of claim 14, wherein said executing instructions operate todetermine a cell rate received by the memory storage device of the datacommunication platform.
 17. The article of claim 14, wherein saidexecuting instructions operate to determine a data signal bandwidthcapability for a dynamic random access memory (DRAM) device.
 18. Thearticle of claim 14, wherein said executing instructions operate tosegment the memory storage device based upon at least a particular bitrate of the plurality data signal ports.
 19. The article of claim 14,wherein said executing instructions operate to segment the storagedevice into a plurality of segments each having a data signal bandwidthcapability substantially similar to the data signal bandwidth capabilityof the memory storage device.
 20. The article of claim 14, wherein saidexecuting instructions operate to segment the memory storage device intoa plurality of segments each dedicated to a particular number of theplurality of data signal ports of the data communication platform. 21.An apparatus comprising: a storage medium having stored therein aplurality of instructions that are machine executable, wherein whenexecuted, said executing instructions operate to receive a data signalat a plurality of data signal ports of a data communication platform,determine a data signal bandwidth capability for a memory storage deviceof the data communication platform, and segment the memory storagedevice to improve utilization of the data signal bandwidth capability ofthe memory storage device of the data communication platform; and aprocessor coupled to the storage medium to execute the instructions. 22.The apparatus of claim 21, wherein said executing instructions operateto determine the data signal bandwidth capability for a network switchengine, the network switch engine implemented as application specificintegrated circuits (ASICs).
 23. The apparatus of claim 21, wherein saidexecuting instructions operate to determine a cell rate received by thememory storage device of the data communication platform.
 24. Theapparatus of claim 21, wherein said executing instructions operate todetermine a data signal bandwidth capability for a dynamic random accessmemory (DRAM) device.
 25. The apparatus of claim 21, wherein saidexecuting instructions operate to segment the memory storage devicebased upon at least a particular bit rate of the plurality data signalports.
 26. The apparatus of claim 21, wherein said executinginstructions operate to segment the storage device into a plurality ofsegments each having a data signal bandwidth capability substantiallysimilar to the data signal bandwidth capability of the memory storagedevice.
 27. The apparatus of claim 21, wherein said executinginstructions operate to segment the memory storage device into aplurality of segments each dedicated to a particular number of theplurality of data signal ports of the data communication platform.